The goal of the HCT is to generate scores that represent the complexity of the constituent
modules of large IC design projects i.e. SOCs.
The design's complexity scores are useful to verification teams so as to efficiently focus
resources based on the dynamic complexity profile
of a design. The scores are a useful tool to guide HDL
designer's refactoring efforts. This data provides an efficient way to "come up to
speed", by pointing you to the most important modules of a legacy design.
Importantly, the complexity scores allow managers to estimate schedules and resources
in a more robust and effective way than any one standard metric can provide
(SLOC for example).
The metrics that compose the score are derived directly from the HDL source code using
a parser. Metrics that are used are chosen to provide a good cross section of complexity.
For example, a measure of the
of a module along with the hierarchy of modules within a module are taken into account
to produce the score. Metrics are based on well established and published methods. After
computing the metrics of a design, they are scaled and then used to create a score
by incorporating the user defined weights (yes, there is a default). In this way, a
set of scores are "tunable" and therefore provide the greatest amount of flexibility
to the user and at the same time are based on standard measurements of the design.
The HDL Complexity Tool is a simple tool to provide measurement data. The driving concept
being that you cannot control what you cannot measure. We intend to use existing research
to develop a tool that performs well on a set of real projects.
Actual defect data will be used to test complexity as a technique to identify risky
components. Real designs will be measured to determine what are the practical uses of hct.
In the end, this tool should be practically useful to anyone designing and/or verifying
a complex hardware project.
|2009-08-28||The HDL Complexity Tool: Interactive HCT Shell
In the upcoming release, we will introduce the interactive shell! This feature will be available by default for interactive sessions with the HCT, but scripts will continue to be able to use command arguments. The benefit of the interactive shell include: an easy to use interface, specialized HCT commands, access to typical BASH shell commands and of course persistence of state determined by input commands. The shell simplifies the interaction between the user and the HCT, thus minimizing the "complexity" of user interaction ;)
|2009-08-20||The HDL Complexity Tool: Module Hierarchy Graphics
In the upcoming release, we will introduce module hierarchy graphics!
This allows users to visualize a design's module instantiation hierarchy
in a tree-like format. All of the currently supported HDLs will be able
to take advantage of this feature.
|2009-08-07||Announcing HCT version 0.7.60!
We are proud to announce beta **VHDL** support! The VHDL parser is bug free and feature complete, but
we need your help to give it a thorough work out. Additionally, we have improved the quality of the
installation process to make it easier to install on Linux, Windows and Mac.
|2009-08-02||Announcing HCT version 0.7.50!
Announcing the HCT version 0.7.50 release!!! This release fully supports Verilog and Cyclicity CDL, with
experimental VHDL support. Our new configuration system makes it much easier to install the HCT on
Windows, Mac and Linux workstations. The parser engine's performance is significantly improved. Various
bug fixes are implemented, most notably correcting flaws in the SLOC and Lines of Comments metrics.
Our project file hierarchy is restructured and finalized.