HDL::Verilog - Class of Verilog language.


Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL, is most commonly used in the design, verification, and implementation of digital logic chips at the Register transfer level (RTL) level of abstraction. It is also used in the verification of analog and mixed-signal circuits.


A description of the syntax in Backus-Naur form (predates the IEEE-1364 standard): http://www.verilog.com/VerilogBNF.html. Also a heavily linked BNF syntax for Verilog 2001 can be found here http://www.externsoft.ch/download/verilog.html.


This document is part of HCT, the Hardware Complexity Tool.

Generated: Fri Jul 17 10:38:47 2009