The HDL Complexity Tool
   

Basics of Output:


What the output means


FILE NAME

The name of the file we are parsing. It is accepted by the parser based on the file extension, which is also used to select the parser's language.

MODULE NAME

A file can contain one or more modules and when a module is encountered it is tracked independently from the file.

IO

The I/O registers declared in the module connecting to other modules. In Verilog this is either an input/output register.

NET

The networks declared in the module connecting to other modules. From Verilog that is: wire, tri, tri1, supply0, wand, triand, tri0, supply1, wor, trior and trireg.

TIME

The amount of wall clock time it took to process the file or module.

CCM

The McCabe Cyclomatic Complexity of a module or file.

SLOC

Source lines of code (SLOC) is a software metric used to measure the size of a software program by counting the number of lines in the text of the program's source code. The most common definition of physical SLOC is a count of lines in the text of the program's source code including comment lines. The blank lines are not counted.

COMMENT LINES

Number of lines of comments.


Output formats


The HCT intends to make it easy for you to use and analyze the data it produces. It supports multiple output formats, such as Comma Separated Value (CSV) to make it easy to import into a spreadsheet or database and a command line tabular format that is easy to read for quick scans of the results. You can output data at various levels of verbosity starting with level 1, which is the most concise.


Output options


Global output options:
-o--output-file=FILE Set output file.
--output-format=FORMAT Output format: terminal, csv. By default terminal.
 
Output options sensitive to language:
--output-level=NUMBER Output level. By default 1.
--output-exclude=LIST Exclude following list of metrics from report. (Should be separated by commas)
--output-levels Print output levels. Only if language set!
--output-metrics print output metrics. Only if language set!
--output-no-modules No modules, only total score.

Output examples


$ perl hct.pl HDL/testsuit/verilog/

Directory: /home/d2rk/projects/hct/branches/0.x/src/HDL/testsuit/verilog

Verilog, 16 file(s)
+--------------------+--------------+------+-------+----------+--------+
| FILENAME           | MODULE       | IO   | NET   | MCCABE   | TIME   |
+--------------------+--------------+------+-------+----------+--------+
| RAM.v                               6      0       4          0.3456 |
|                      RAM            6      0       4                 |
+----------------------------------------------------------------------+
| one_day2.v                          0      0       2          0.0808 |
|                      one_day2       0      0       2                 |
+----------------------------------------------------------------------+
| modules.v                           1      0       2          0.0257 |
|                      m1             1      0       1                 |
|                      m2             0      0       1                 |
+----------------------------------------------------------------------+
| hello_world.v                       0      0       1          0.0276 |
|                      hello_world    0      0       1                 |
+----------------------------------------------------------------------+
| GPR.v                               5      0       3          0.1889 |
|                      GPR            5      0       3                 |
+----------------------------------------------------------------------+
| RAMB16_S9.v                         6      5       12         4.6911 |
|                      RAMB16_S9      6      5       12                |
+----------------------------------------------------------------------+
| first_counter_tb.v                  0      1       1          0.0533 |
|                      first_counte   0      1       1                 |
+----------------------------------------------------------------------+
| first_counter.v                     4      3       3          0.1474 |
|                      first_counte   4      3       3                 |
+----------------------------------------------------------------------+
| Sys430.v                            7      12      9          0.9128 |
|                      Sys430         2      12      5                 |
|                      LEDTest        5      0       4                 |
+----------------------------------------------------------------------+
| encoder_using_if.v                  3      0       17         0.3644 |
|                      encoder_usin   3      0       17                |
+----------------------------------------------------------------------+
| Case.v                              0      0       18         0.2084 |
|                      case           0      0       18                |
+----------------------------------------------------------------------+
| S430.v                              11     4       1          0.4315 |
|                      S430           11     4       1                 |
+----------------------------------------------------------------------+
| one_day3.v                          0      0       4          0.0753 |
|                      one_day3       0      0       4                 |
+----------------------------------------------------------------------+
| Multiplier.v                        7      4       1          0.3370 |
|                      Multiplier     7      4       1                 |
+----------------------------------------------------------------------+
| comment.v                           0      0       1          0.0185 |
|                      comment        0      0       1                 |
+----------------------------------------------------------------------+
| encoder_using_case                  3      0       16         0.2450 |
|                      encoder_usin   3      0       16                |
+----------------------------------------------------------------------+