We've numerous requests to implement VHDL in the HCT. So alright, we'll do it ;) We're currently planning a VHDL parser module to complement the existing Verilog and CDL parsers. We plan to release a beta version within the next 2 to 3 months. Want it faster? Then please donate your time to give us a hand!

Added support of cycle description language (CDL). Also available new output level for languages Verilog and CDL to produce SLOC information.

This release is the final fully modified version of the tool. From this point on, we expect to simply add to the existing functionality.

In this version we support only Verilog, but the CDL language will be coming soon. In the upcoming version, we will extend the API documentation as well as include instructions on how to add a new language of your own.

The HCT project has grown, so we need your help! Please email us today if you are interested in joining this exciting project.

This is a completely redesigned tool that produces stable complexity metrics from Verilog and Cyclicity CDL projects. Mixed code is not a problem and both files and modules are supported. We have focused on useful complexity metrics in several output formats and tried to improve performance as well. This release has been fielded and we are gathering feedback. Please join this alpha deployment stage and let us know what you need.

Now, not only software engineers can enjoy the benefits of complexity analysis! The HDL Complexity Tool applies state of the art complexity analysis to complex hardware designs. The 0.0.1 release is an early alpha release targeting Verilog and Cyclicity CDL. Our team members continue to develop the practical aspects of complexity analysis using this and future versions of HCT on real world projects. Do you want to help up meet our goal of an EFFECTIVE open source complexity analysis tool for your design flow? Then please give it a try and let us know what you think!